module lab4 (
    input clk,
    input rst,
    input [3:0] key_row,
    input [3:0] k,
    input [2:0] s,
    input cin,
    output [3:0] key_col,
    output [7:0] seg,
    output [2:0] sel,
    output overflow
);

  wire is_pressed;

  wire [3:0] val;
  key u_key (
      clk,
      rst,
      key_row,
      key_col,
      val,
      is_pressed
  );

  wire [ 7:0] x;
  wire [ 7:0] y;
  wire [ 7:0] res;
  reg  [31:0] data;

  alu u_alu (
      clk,
      rst,
      s,
      x,
      y,
      cin,
      res,
      overflow
  );

  assign x = data[31:24];
  assign y = data[23:16];

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      data <= 32'd0;
    end else if (is_pressed) begin
      if (k[0]) begin
        data[31:28] <= val;
      end else if (k[1]) begin
        data[27:24] <= val;
      end else if (k[2]) begin
        data[23:20] <= val;
      end else if (k[3]) begin
        data[19:16] <= val;
      end
      data[7:0] <= res;
    end else begin
      data[7:0] <= res;
    end
  end

  display u_display (
      clk,
      rst,
      data,
      seg,
      sel
  );

endmodule
